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asahi kasei [AK5383] m0049-e-03 2000/4 - 1 - general description the AK5383 is a 24bit, 128x oversampling 2ch a/d converter for professional digital audio systems. the modulator in the AK5383 uses the new developed enhanced dual bit architecture. this new architecture achieves the wide dynamic range, while keeping much the same superior distortion characteristics as conventional single bit way. the AK5383 performs 110db dynamic range, so the device is suitable for professional studio equipment such as digital mixer, digital vtr etc. features p enhanced dual bit adc p sampling rate: 1khz~108khz p full differential inputs p s/(n+d): 103db p dr: 110db p s/n: 110db p high performance linear phase digital anti-alias filter passband: 0~21.768khz(@fs=48khz) ripple: 0.001db stopband: 110db p digital hpf & offset calibration for offset cancel p power supply: 5v 5%(analog), 3~5.25v(digital) p power dissipation: 210mw p package: 28pin sop, vsop p ak5393 pin compatible lrck vrefl gndl sclk smode1 fsync serial output interface smode2 dgnd va agnd bgnd cal rst vd controller sdata mclk dfs hpfe zcal ainr- gndr delta-sigma modulator delta-sigma modulator voltage reference voltage reference decimation filter decimation filter hpf hpf calibration sram vcoml ainl+ ainl- ainr+ vcomr vrefr 12 11 14 13 16 15 19 17 18 8 7 10 9 21 22 23 27 28 26 24 25 6 5 4 3 2 1 enhanced dual bit ds 96khz 24-bit adc AK5383
asahi kasei [AK5383] m0049-e-03 2000/4 - 2 - n ordering guide AK5383vs C10 ~ +70 c 28pin sop AK5383vf C40 ~ +85 c 28pin vsop akd5383 AK5383 evaluation board n pin layout 6 5 4 3 2 1 vrefl gndl ainl+ vcoml ainl- zcal vd 7 dgnd 8 top view 10 9 cal rst smode2 11 smode1 12 13 14 lrck sclk vrefr gndr vcomr ainr+ ainr- va agnd bgnd test hpfe dfs mclk 23 24 25 26 27 28 22 21 19 20 18 17 16 15 fsync sdata n compatibility with ak5393 ak5393 AK5383 s/(n+d) 105db 103db dr, s/n 117db 110db
asahi kasei [AK5383] m0049-e-03 2000/4 - 3 - pin/function no. pin name i/o function 1 vrefl o lch reference voltage pin, 3.75v normally connected to gndl with a 10f electrolytic capacitor and a 0.1f ceramic capacitor. 2 gndl - lch reference ground pin, 0v 3 vcoml o lch common voltage pin, 2.75v 4 ainl+ i lch analog positive input pin 5 ainl- i lch analog negative input pin 6 zcal i zero calibration control pin this pin controls the calibration reference signal. "l": vcoml and vcomr "h": analog input pins ( ainl , ainr ) 7 vd - digital power supply pin, 3.3v 8 dgnd - digital ground pin, 0v 9 cal o calibration active signal pin "h" means the offset calibration cycle is in progress. offset calibration starts when rst goes "h". cal goes "l" after 8704 lrck cycles for dfs="l", 17408 lrck cycles for dfs ="h". 10 rst i reset pin when "l", digital section is powered-down. upon returning "h", an offset calibration cycle is started. an offset calibration cycle should always be initiated after power-up. 11 12 smode2 smode1 i i serial interface mode select pin msb first, 2's compliment. smode2 smode1 mode lrck l l slave mode : msb justified : h/l l h master mode : similar to i 2 s : h/l h l slave mode : i 2 s : l/h h h master mode : i 2 s : l/h 13 lrck i/o left/right channel select clock pin lrck goes "h" at smode2="l" and "l" at smode2="h" during reset when smode1 "h".
asahi kasei [AK5383] m0049-e-03 2000/4 - 4 - 14 sclk i/o serial data clock pin data is clocked out on the falling edge of sclk. slave mode: sclk requires more than 48fs clock. master mode: sclk outputs a 128fs(dfs="l") or 64fs(dfs="h") clock. sclk stays "l" during reset. 15 sdata o serial data output pin msb first, 2's complement. sdata stays "l" during reset. 16 fsync i/o frame synchronization signal pin slave mode: when "h", the data bits are clocked out on sdata. in i 2 s mode, fsync is dont care. master mode: fsync outputs 2fs clock. fsync stays "l" during reset. 17 mclk i master clock input pin 256fs at dfs="l", 128fs at dfs="h". 18 dfs i double speed sampling mode pin "l": normal speed "h": double speed 19 hpfe i high pass filter enable pin "l": disable "h": enable 20 test i test pin ( pull-down pin) should be connected to gnd. 21 bgnd - substrate ground pin, 0v 22 agnd - analog ground pin, 0v 23 va - analog supply pin, 5v 24 ainr- i rch analog negative input pin 25 ainr+ i rch analog positive input pin 26 vcomr o rch common voltage pin, 2.75v 27 gndr - rch reference ground pin, 0v 28 vrefr o rch reference voltage pin, 3.75v normally connected to gndr with a 10f electrolytic capacitor and a 0.1f ceramic capacitor note: all digital inputs should not be left floating.
asahi kasei [AK5383] m0049-e-03 2000/4 - 5 - absolute maximum ratings (agnd,bgnd,dgnd=0v; note 1) parameter symbol min max units power supplies: analog digital |bgnd-dgnd| (note 2) va vd d gnd -0.3 -0.3 - 6.0 6.0 0.3 v v v input current, any pin except supplies iin - 10 ma analog input voltage vina -0.3 va+0.3 v digital input voltage vind -0.3 vd+0.3 v ambient temperature (power applied) AK5383vs AK5383vf ta ta -10 -40 70 85 c c storage temperature tstg -65 150 c notes: 1. all voltages with respect to ground. 2. agnd, bgnd and dgnd must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd,bgnd,dgnd=0v; note 1) parameter s ymbol min typ max units power supplies: analog (note 3) digital va vd 4.75 3.0 5.0 3.3 5.25 5.25 v v notes:1. all voltages with respect to ground. 3. the power up sequence between va and vd is not critical. * akm assumes no responsibility for the usage beyond the conditions in this data sheet.
asahi kasei [AK5383] m0049-e-03 2000/4 - 6 - analog characteristics (ta=25 c; va=5.0v; vd=3.3v; agnd,bgnd,dgnd=0v; fs=48khz; signal frequency=1khz; 24bit output; measurement frequency=10hz~20khz; unless otherwise specified) parameter min typ max units resolution 24 bits analog input characteristics: fs=48khz -1dbfs -20dbfs -60dbfs 96 - - 103 87 47 db db db s/(n+d) fs=96khz bw=40khz -1dbfs -20dbfs -60dbfs 93 - - 100 81 41 db db db dynamic range (-60dbfs with a-weighted ) 105 110 db s/n ( a-weighted ) 105 110 db interchannel isolation 110 120 db interchannel gain mismatch 0.1 0.5 db gain drift 150 ppm/ c offset error after calibration, hpf=off after calibration, hpf=on 200 1 1000 lsb 24 lsb 24 offset drift (hpf=off) - 10 - lsb 24 / c offset calibration range (hpf=off) 50 mv input voltage (ain+)-(ain-) 2.3 2.45 2.6 v input impedance 8 14 k w power supplies power supply current va vd (fs=48khz; dfs=l) (fs=96khz; dfs=h) 38 6 9 54 9 14 ma ma ma power dissipation 210 300 mw power supply rejection (note 4) 70 db note: 4. psrr is applied to va, vd with 1khz, 20mvpp.
asahi kasei [AK5383] m0049-e-03 2000/4 - 7 - filter characteristics(fs=48khz) (ta=25 c; va=5.0v 5%; vd=3.0~5.25v; fs=48khz, dfs=l) parameter symbol min typ max units adc digital filter(decimation lpf): passband (note 5) pb 0 21.768 khz stopband (note 5) sb 26.232 khz passband ripple pr 0.001 db stopband attenuation (note 6) sa 110 db group delay distortion d gd 0 us group delay (note 7) gd 38.7 1/fs adc digital filter(hpf): frequency response (note 5) -3db -0.1db fr 1.0 6.5 hz hz filter characteristics(fs=96khz) (ta=25 c; va=5.0v 5%; vd=3.0~5.25v; fs=96khz, dfs=h) parameter symbol min typ max units adc digital filter(decimation lpf): passband (note 5) pb 0 43.536 khz stopband (note 5) sb 52.464 khz passband ripple pr 0.003 db stopband attenuation (note 8) sa 110 db group delay distortion d gd 0 us group delay (note 7) gd 38.8 1/fs adc digital filter(hpf): frequency response (note 5) -3db -0.1db fr 2.0 13.0 hz hz notes: 5. the passband and stopband frequencies scale with fs. 6. the analog modulator samples the input at 6.144mhz for an output word rate of 48khz. there is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 6.144mhz 21.768khz, where n=1,2,3). 7. the calculating delay time which occurred by digital filtering. this time is from the input of analog signal to setting the 24bit data of both channels to the output register. 40.7/fs(dfs = "l"),40.8/fs(dfs = "h")typ. at hpf:on. 8. the analog modulator samples the input at 6.144mhz for an output word rate of 96khz. there is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 6.144mhz 43.536khz, where n=1,2,3).
asahi kasei [AK5383] m0049-e-03 2000/4 - 8 - digital characteristics (ta=25 c; va=5.0v 5%; vd=3.0 ~ 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%vd - - - - 30%vd v v high-level output voltage iout=-20a low-level output voltage iout=20a voh vol vd-0.1 - -- 0.1 v v input leakage current iin - - 10 a switching characteristics (ta=25 c; va=5.0v 5%; vd=3.0 ~ 5.25v; c l =20pf) parameter symbol min typ max units control clock frequency master clock 256fs: pulse width low pulse width high serial data output clock (sclk) channel select clock (lrck) duty cycle fclk tclkl tclkh fslk fs 0.256 29 29 1 25 12.288 6.144 48 13.824 6.912 108 75 mhz ns ns mhz khz % serial interface timing (note 9) slave mode(smode1="l") sclk period sclk pulse width low pulse width high sclk falling to lrck edge (note 10) lrck edge to sdata msb valid sclk falling to sdata valid sclk falling to fsync edge master mode(smode1="h") sclk frequency (dfs="l") sclk frequency (dfs="h") duty cycle fsync frequency duty cycle sclk falling to lrck edge lrck edge to fsync rising sclk falling to sdata valid sclk falling to fsync edge tslk tslkl tslkh tslr tdlr tdss tsf fslk fslk ffsync tslr tlrf tdss tsf 144.7 65 65 -45 -45 -20 -20 128fs 64fs 50 2fs 50 1 45 45 45 45 20 45 20 ns ns ns ns ns ns ns hz hz % hz % ns tslk ns ns reset/calibration timing rst pulse width rst falling to cal rising rst rising to cal falling (note 11) rst rising to sdata valid (note 11) trtw trcr trcf trtv 150 8704 8960 50 ns ns 1/fs 1/fs notes: 9. refer to serial data interface. 10. specified lrck edges not to coincide with the rising edges of sclk. 11. the number of the lrck rising edges after rst brought high at dfs="l". the value is in master mode. in slave mode it becomes one lrck clock(1/fs) longer. when dfs="h", trcf=17408 and trtv=17920.
asahi kasei [AK5383] m0049-e-03 2000/4 - 9 - n timing diagram lrck sclk sdata tdss tslr tslkl tslkh tslk tdlr msb msb-1 msb-2 serial data timing (slave mode, fsync="h") lrck sclk tslr tsf sdata tdlr msb d1 d0 tsf tdss fsync serial data timing (slave mode) lrck sclk sdata tdss tslr tslkl tslkh tslk msb msb-1 tdss serial data timing (i 2 s slave mode, fsync = don't care)
asahi kasei [AK5383] m0049-e-03 2000/4 - 10 - lrck sclk tslr tsf sdata msb-1 tsf tdss msb fsync tlrf serial data timing (master mode & i 2 s master mode, dfs ="l") rst sdata trtv trcr cal trtw trcf reset & calibration timing
asahi kasei [AK5383] m0049-e-03 2000/4 - 11 - operation overview n system clock input the external clocks which are required to operate the AK5383 are mclk, lrck(fs), sclk. mclk should be synchronized with lrck but the phase is free of care. mclk should be 256fs in normal sampling mode(dfs="l") and double sampling mode needs 128fs as mclk. table 2 illustrates standard audio word rates and corresponding frequencies used in the AK5383. as the AK5383 includes the phase detect circuit for lrck, the AK5383 is reset automatically when the synchronization is out of phase by changing the clock frequencies. therefore, the reset is only needed for power-up. all external clocks must be present unless rst ="l", otherwise excessive current may result from abnormal operation of internal dynamic logic. speed normal(dfs ="l") double(dfs ="h") lrck (max) 54khz 108khz sclk ~128fs ~64fs mclk 256fs 128fs table 1. system clocks fs mclk sclk 32.0khz 8.1920mhz 4.0960mhz 44.1khz 11.2896mhz 5.6448mhz 48.0khz 12.2880mhz 6.1440mhz 96.0khz 12.2880mhz 6.1440mhz table 2. examples of system clock frequency n serial data interface the AK5383 supports four serial data formats which can be selected via smode1 and smode2 pins(table 3). the data format is msb-first, 2's complement. figure smode2 smode1 mode lrck figure 1 l l slave mode lch = h, rch =l figure 2 l h master mode lch =h, rch =l figure 3 h l i 2 s slave mode lch =l, rch =h figure 4 h h i 2 s master mode lch =l, rch =h table 3. serial i/f format
asahi kasei [AK5383] m0049-e-03 2000/4 - 12 - lrck(i) sclk ( i ) 012 2021232415 01 20222325 0 1 25 22 21 24 lch data rch data sdata ( o ) 23 22 23 21 7 4 2 43 20 1 21 22 310 3 23 fsync( i ) fsync ( i ) 23 23 22 5 3 54 310 2 22 4210 22 23 23 sdata ( o ) 23:msb,0:lsb figure 1. serial data timing (slave mode) lrck(o) sclk ( o ) 0 1 2 20 21 23 24 15 34 3 20 21 23 0 1 25 22 2 22 3 01 fsync(o) 23 23 5 3 54 310 2 22 4210 23 sdata ( o ) lch data 33 25 24 33 34 22 23:msb,0:lsb rch data figure 2. serial data timing (master mode, dfs="l") lrck ( i ) sclk(i) 0 1 2 1920 2223 0 1 19 2122 24 0 1 24 21 20 23 3 23 23 23 22 6 4 65 421 3 22 5321 23 sdata(o) lch data rch data 23:msb,0:lsb 0 0 figure 3. serial data timing (i 2 s slave mode, fsync: dont care.) lrck ( o ) sclk ( o ) 0 1 2 20 21 23 24 15 34 3 20 21 23 0 1 25 22 2 22 3 01 fsync ( o ) 23 23 23 5 3 54 310 2 22 4210 23 sdata( o) lch data rch data 33 25 24 33 34 22 23:msb,0:lsb figure 4. serial data timing (i 2 s master mode, dfs="l")
asahi kasei [AK5383] m0049-e-03 2000/4 - 13 - n offset calibration when rst pin goes to "l", the digital section is powered-down. upon returning "h", an offset calibration cycle is started. an offset calibration cycle should always be initiated after power-up. during the offset calibration cycle, the digital section of the part measures and stores the values of calibration input of eac h channel in registers. the calibration input value is subtracted from all future outputs. the calibration input may be obtained from either the analog input pins (ain+/-) or the vcom pins depending on the state of the zcal pin. with zcal "h", the analog input pin voltages are measured, and with zcal "l", the vcom pin voltages are measured. the cal output is "h" during calibration. n digital high pass filter the AK5383 also has a digital high pass filter for dc offset cancel. the cut-off frequency of the hpf is 1hz at fs=48khz and also scales with sampling rate(fs).
asahi kasei [AK5383] m0049-e-03 2000/4 - 14 - system design figure 5 and 6 show the system connection diagram. an evaluation board[akd5383] is available which demonstrates the optimum layout, power supply arrangements and measurement results. vrefl 1 gndl 2 vcoml 3 ainl+ 4 ainl- 5 zcal 6 vd 7 dgnd 8 cal 9 rst 10 smode2 11 smode1 12 vrefr 28 gndr 27 vcomr 26 ainr+ 25 ainr- 24 va 23 agnd 22 bgnd 21 test 20 hpfe 19 dfs 18 mclk 17 0.1 10 + AK5383 13 14 16 15 lrck sclk fsync sdata 0.22 lch+ +3.3~5v digital rch+ rch- 0.22 reset & cal control 10 + 0.1 system controller mode select +5v analog + 0.1 10 0.1 10 + lch- fs 256fs analog ground system ground @fs=48k figure 5. typical connection diagram notes: - lrck = fs, sclk=64fs. - power lines of va and vd should be distributed separately from the point with low impedance of regulator etc. - agnd, bgnd and dgnd must be connected to the same analog ground plane. - all input pins except pull-down/pull-up pins should not be left floating. analog ground digital ground system controller vrefl 1 gndl 2 vcoml 3 ainl+ 4 ainl- 5 zcal 6 vd 7 dgnd 8 cal 9 rst 10 smode2 11 smode1 12 vrefr 28 gndr 27 vcomr 26 ainr+ 25 ainr- 24 va 23 agnd 22 bgnd 21 test 20 hpfe 19 dfs 18 mclk AK5383 17 13 14 16 15 lrck sclk fsync sdata figure 6 ground layout
asahi kasei [AK5383] m0049-e-03 2000/4 - 15 - 1. grounding and power supply decoupling the AK5383 requires careful attention to power supply and grounding arrangements. analog ground and digital ground should be separate and connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK5383 as possible, with the small value ceramic capacitor being the nearest. 2. on-chip voltage reference and vcom the reference voltage for a/d converter is a differential voltage between the vrefl/r output voltage and the gndl/r input voltage. the gndl/r are connected to agnd and a 10uf electrolytic capacitor parallel with a 0.1uf ceramic capacitor between the vrefl/r and the gndl/r eliminate the effects of high frequency noise. especially a ceramic capacitor should be as near to the pins as possible. and all digital signals, especially clocks, should be kept away from the vrefl/r pins in order to avoid unwanted coupling into the AK5383. no load current may be taken from the vrefl/r pins. vcom is a common voltage of the analog signal. in order to eliminate the effects of high frequency noise, a 0.22uf ceramic capacitor should be connected as near to the vcom pin as possible. and all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the AK5383. no load current may be drawn from the vcom pin. 3. analog inputs analog signal is differentially input into the modulator via the ain+ and the ain- pins. the input voltage is the difference between ain+ and ain- pins. the full-scale of each pin is nominally 2.45vpp(typ). the AK5383 can accept input voltages from agnd to va. the adc output data format is 2's complement. the output code is 7fffffh(@24bit) for input above a positive full scale and 800000h(@24bit) for input below a negative full scale. the ideal code is 000000h (@24bit) with no input signal. the dc offset is removed by the offset calibration. the AK5383 samples the analog inputs at 128fs(6.144mhz @fs=48khz,dfs="l"). the digital filter rejects noise above the stop band except for multiples of 128fs. a simple rc filter may be used to attenuate any noise around 128fs and most audio signals do not have significant energy at 128fs. the AK5383 accepts +5v supply voltage. any voltage which exceeds the upper limit of va+0.3v and lower limit of agnd-0.3v and any current beyond 10ma for the analog input pins(ain+ /-) should be avoided. excessive currents to the input pins may damage the device. hence input pins must be protected from signals at or beyond these limits. use caution specially in case of using 15v in other analog circuits.
asahi kasei [AK5383] m0049-e-03 2000/4 - 16 - figure 7shows an input buffer circuit example 1. this is a full-differential input buffer circuit with an inverted-amp (gain :-10db). the capacitor of 10nf between ain+ /- decreases the clock feed through noise of m odulator, and composes a 1st order lpf(fc=360khz) with 22ohm resistor before the capacitor. this circuit also has a 1st order lpf(fc=370khz) composed of op-amp. in this example, the internal offset is removed by self calibration. the evaluation board should be referred about the detail. 4.7k - + - + 22 3k 910 - + 22 910 AK5383 ain+ ain- cal zcal analog in 8.1vpp "l" at self calibration 47 47 njm5532 va= 5v vp= 15v 4.7k 10 + 10k 10k 0.1 bias va+ 2.45vpp 2.45vpp vp+ vp- bias 470p 3k 470p bias 10n figure 7 differential input buffer example 1 figure 8 shows an input buffer circuit example 2. (1 st order hpf; fc=0.66hz, table 4, 1 st order lpf; fc=590khz, gain=- 14db, table 5). the analog signal is able to input through xlr or bnc connectors. (short jp1 and jp2 for bnc input, open jp1 and jp2 for xlr input) . the input level of this circuit is +/-12.4vpp (AK5383: +/-2.45vpp typ.). 180 100 bias vin+ AK5383 ain+ - + va 1.5n 1k 10k 22u 180 vin- AK5383 ain- - + 1k 22u 10k 0.1u 10u 4.7k 4.7k xlr bnc - + 4.7k 4.7k jp2 jp1 njm5534 njm5534 njm5534 2.45vpp 2.45vpp 12.4vpp 12.4vpp figure 8 differential input buffer example 2 fin 1hz 10hz frequency response -1.56db -0.02db table 4. frequency response of hpf fin 20khz 40khz 6.144mhz frequency response -0.005db -0.02db -15.6db table 5. frequency response of lpf
asahi kasei [AK5383] m0049-e-03 2000/4 - 17 - package (AK5383vs) 0 - 10 0.10 0.15-0.05 1.095typ 18.7 0.3 28pin sop ( unit: mm ) 7.5 0.2 0.75 0.2 +0.1 10.4 0.3 2.2 0.1 1.27 0.12 m +0.1 0.1-0.05 0.4 0.1 n package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
asahi kasei [AK5383] m0049-e-03 2000/4 - 18 - package (AK5383vf) 1.0 0.1 0.1 0 -10 detail a seating plane note: dimension "*" does not include mold flash. 0.10 0.15-0.05 0.22 0.1 0.65 *9.8 0.2 1.25 0.2 a 1 14 15 28 28pin vsop ( unit: mm ) *5.6 0.2 7.6 0.2 0.5 0.2 +0.1 0.675 n package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
asahi kasei [AK5383] m0049-e-03 2000/4 - 19 - marking (AK5383vs) akm AK5383vs xxxbyyyyc japan xxxxbyyyyc: date code identifier xxxb: lot number (x : digit number, b : alpha character ) yyyyc: assembly date (y : digit number c : alpha character)
asahi kasei [AK5383] m0049-e-03 2000/4 - 20 - marking (AK5383vf) akm AK5383vf xxxbyyyyc xxxxbyyyyc: date code identifier xxxb: lot number (x : digit number, b : alpha character ) yyyyc: assembly date (y : digit number c : alpha character) important notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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